Silicon Engineering Manager, Design and Verification

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in ASIC design verification methodology.
• 4 years of experience in leading/managing IP/Subsystem verification teams.
• Experience in UVM based IP and Subsystem/SoC verification.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in PSS (Portable Test and Stimulus Standard), formal or emulation based SimXL (Simulation Acceleration) methodologies.
• Familiarity with industry-standard EDA tools and methodologies.
• Track record to drive design verification methodology improvements in the team.
• Strong programming skills in Verilog, SystemVerilog, and Perl/Python.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Lead and manage verification activities for complex subsystems and/or SoC.
• Develop all aspects of logic verification infrastructure and methodology for complex mobile SOC IP or subsystem blocks.
• Collaborate with design teams to ensure seamless integration of verification methodology into the design process.
• Optimize and improve verification methodologies to increase efficiency and effectiveness.
• Collaborate with both external and internal CAD teams to develop new verification solutions that can improve the quality and efficiency.

Collaborate with both external and internal CAD teams to develop new verification solutions that can improve the quality and efficiency.